The present invention relates to a bus control device and bus control system, particularly to a bus control device in which cyclic data transfer is performed with units in the bus control device via a serial bus to reduce the traffic amount of a parallel bus and a bus control system in which data transfer is performed with units outside the bus control device by a serial bus.
FIG. 23 is a schematic diagram showing a connection of a control board in a conventional bus control device and external units. In the drawing, numeral 1a denotes an Numeral Control (NC) device unit, 2 denotes an NC device power supply, 3a denotes an NC control board, 4 denotes an internal I/O unit of the NC device unit 1a, 5 denotes an operation panel, 6 denotes a personal computer, 7 denotes a manual handle for manually operating a machine, 8 denotes a mechanical operation panel, 10 denotes a servo amplifier/main shaft amplifier unit (hereinafter referred to as the drive controller), 11 denotes a servo motor encoder, 12 denotes a servo motor, 14 denotes a main shaft motor, 15 denotes a main shaft motor encoder, 20a denotes another servo amplifier/inverter for performing positioning and the like, 21 denotes a motor controlled by the servo amplifier/inverter 20a, 22 denotes a position detecting encoder as a position detector of the motor 21, 30a denotes a sensor input unit, 40 denotes a remote I/O unit installed separately from the NC device unit 1a to perform I/O control, 60a denotes a serial cable for connecting the servo amplifier/inverter 20a and position detecting encoder 22 via serial signals, 60b denotes a serial cable for serially transmitting position data detected by the position detecting encoder 22 to the NC device unit 1a, 60c denotes a serial cable for connecting the NC device unit 1a and sensor input unit 30a, 60d denotes a serial cable for connecting the NC device unit 1a and remote I/O units 40 via serial communication, and 60e denotes a serial cable for connecting the NC device unit 1a and drive controller 10 via serial communication. In the conventional bus control device shown in FIG. 23, the NC control board 3a, drive controller 10, remote I/O units 40, sensor input unit 30a, and position detecting encoder 22 are connected to the bus control device via individual cables. Since a large number of cables need to be connected, a large connector mounting space is required. Thus, it is difficult to miniaturize the bus control device.
FIG. 24 shows the bus constitution of the conventional bus control device. FIG. 24(A) is a package view of the conventional bus control device. And FIG. 24B is an explanatory view of the bus control system in which communication is performed between the bus control device and the remote I/O units 40. In the NC device unit 1a shown in FIG. 24(a), the NC control board 3a is connected to the internal I/O units 4 via a parallel bus 70, and connected to the remote I/O units 40 via the serial cable 60d. The parallel bus 70 of the conventional bus control device is of a system for handshaking the parallel data. It is composed of a parallel address bus, a data bus, and a plurality of control signal conductors. Specifically, in the bus control device, the internal I/O units 4 for I/O controlling proximate control objects or machines and the NC control board 3a are connected via the parallel bus 70. The I/O control is executed on remote control objects or machines via the remote I/O units 40 connected to the serial cable.
The operation of the bus control system will be described next. It is known that in a general parallel bus control system, specified data are read/written from/to memories and registers provided with specified addresses based on a plurality of address signals, data signals, and control signals. The description of those signals is omitted. The bus control device itself performs a cyclic I/O control in accordance with the characteristics of the control objects. In this case, the internal CPU of the NC control board 3a performs cyclic data transmission/reception with the internal I/O units 4 and remote I/O units 40 via the parallel bus 70. Therefore, when the parallel bus 70 is used by the main controller of the NC control board 3a and the internal I/O units 4 to transfer data, the number of signal wires for the internal I/O units 4 is increased. As a result, it becomes more difficult to miniaturize the bus control device. Additionally, since a plurality of signal conductors is to be controlled, the cost of the internal I/O units 4 is increased. A further problem arises when not all the signal conductors are normal, operational defects are caused, and reliability is impaired.
FIG. 25 is a block diagram showing interfaces between a master CPU module 101e in the NC control board 3a and various I/O units. In FIG. 25, numeral 130a denotes a drive controller interface on the side of the NC device unit 1a for controlling communication between a master CPU module 101e and a drive controller 10, 131 denotes a sending memory for holding data to be transmitted to the drive controller 10, 132 denotes a receiving memory for holding data received from the drive controller 10, 133 denotes a send controller for performing transmission to the drive controller 10, 134 denotes a receive controller for receiving data from the drive controller 10, 135 denotes a send timing control register for controlling a transmission timing for the drive controller 10, 136 denotes a receive status control register for holding a reception result status from the drive controller 10, 140a denotes a remote I/O interface on the side of the NC device unit 1a for performing communication with the master CPU module 101e and remote I/O unit 40 in the same manner as the drive controller interface 130a, 141 denotes a sending register for holding data to be transmitted to the remote I/O unit 40, 142 denotes a receiving register for holding data received from the remote I/O unit 40, 143 denotes a send controller for performing transmission to the remote I/O unit 40, 144 denotes a receive controller for receiving data from the remote I/O unit 40, 145 denotes a send timing control register for controlling transmission timings to the remote I/O unit 40, 146 denotes a receive status controller for holding a reception result status from the remote I/O unit 40, 150a denotes a position detecting encoder interface on the side of the NC device unit 1a for receiving position detection data outputted by the position detecting encoder 22 via the servo amplifier/inverter unit 20, 151 denotes a position detecting encoder receiver for receiving a serial transmission frame including position information from the position detecting encoder, 152 denotes a receiving register for holding data received by the position detecting encoder receiver 151, 160a denotes a sensor input interface for receiving sensor input information from the external sensor input unit 30a, 161 denotes a pulse differentiating circuit for differentiating signals from the sensor input unit 30, 162 denotes a sensor measuring counter for measuring sensor input timings, 163 denotes a counter holding register for holding counter contents or values of the sensor measuring counter 162 based on the signals from the pulse differentiating circuit 161, and 164 denotes a sensor interrupt controller for generating interrupt for the master CPU module 101e by sensor inputs. The master CPU module 101e controls the interfaces 130a, 140a, 150a, 160a, while the parallel bus 70 connects the master CPU module 101e with the interfaces 130a, 140a, 150a, 160a. 
The operation of the remote I/O interface 140a is described next. When the master CPU module 101e places the data to be outputted to the remote I/O unit 40 in the sending register 141, the send controller 143 automatically follows the timing sequence stored in the send timing control register 145 for data transmission. The send controller 143, following the timing sequence using its internal timer, reads the content of the sending register 141, encapsulates the content in a transmission frame, and transmits the frame to the remote I/O unit 40. When the transmission frame is received by the remote I/O unit 40, and the reception is normally completed, the remote I/O unit 40 transmits output signals to the outside based on the received data. When reception of the reception frame from the master CPU module 101e is normally completed, and after the internal timer of the remote I/O unit 40 indicates that a time for transmitting some bytes at a transmission rate has elapsed, the communication controller on the side of the remote I/O unit 40 assembles the data based on input signals on the remote I/O unit 40 into a transmission frame for transmission to the NC device unit 1a. The frame is transmitted to the receive controller 144 on the side of the control device, and written in the receiving register 142. When the master CPU module 101e reads the frame from the receiving register 142, it recognizes the frame as the input from the remote I/O unit 40.
The data transmitting/receiving operation between the drive controller interface 130a and the drive controller 10 is described next. In the NC device 1a, a program for processing an object is inputted beforehand in the NC control board 3a. The master CPU module 101e decodes the program and prepares an operation command. The operation command is transmitted to the drive controller 10. In response to the instruction from the master CPU module 101e and the timing sequence in the send timing control register 135a, the send controller 133 reads the operation command data from the sending memory 131, assembles a transmission frame, and transmits the frame. The drive controller 10 operates the servo motor 12 and the main shaft motor 14 based on the operation command from the master CPU module 101e. Additionally, the drive controller 10 returns motor position detection information and status information indicating a state of drive controller 10 and the like to the master CPU module 101e. The motor position detection information, status information indicating the state of drive controller 10, and another data transmitted from the drive controller 10 are stored in the receiving memory 132 via the receive controller 134. The data read by the master CPU module 101e is recognized as input from the drive controller 10. Here the description of operation of the position detecting encoder interface 150a and sensor input interface 160a is omitted, but by repeating the above-mentioned procedure, the NC device can process even a complicated configuration in accordance with the program. In the bus control device of the conventional NC device, the transfer of all data inside the NC device unit 1a depends solely on the parallel bus 70. Since the number of wires inside the NC device unit 1a is increased, miniaturization is difficult. Additionally, there is a problem that a high bus traffic performance is necessary.
The prior art solution to the high bus traffic problem is disclosed in Japanese Patent Application Laid-open No. 264351/1990. In that solution, there are provided a serial bus as an internal bus, and serial and parallel buses as backplane buses, so that the bus is selected in accordance with the characteristics of a function module to reduce the data traffic amount of the parallel bus. However, the publication discloses the control content of the serial and parallel buses, but does not disclose that the serial bus is applied in various manners in accordance with installation conditions and characteristics of each unit.
Therefore, the present invention provides a bus control device and bus control system to solve the following conventional problems.
Problem 1: When data transfer to the I/O unit requires cyclic data transfers inside and outside the bus control device and the parallel bus inside the bus control device is occupied, an obstruction to enhancement of performance of the bus control device results. An object of the present invention is to provide a bus control device in which internal and external I/O units connected to the bus control device and requiring cyclic data transfers are provided with a serial bus to reduce the data traffic amount of a parallel bus and to enhance the performance of the bus control system.
Problem 2: Since cyclic data transfer is necessary for the interface of the I/O unit provided on the bus control device itself, and processing is performed by interrupting the data transfer to the other I/O units, abilities of CPU and control bus of the bus control device are deteriorated with frequent interrupts. An object of the present invention is to provide a bus control device comprising a first serial bus for performing cyclic data communication and a second serial bus for performing asynchronous data communication, in which when the cyclic data communication is necessary, processing can be performed by the first serial bus without interrupting the transmission/reception of the second serial bus.
Problem 3: Generally, the external I/O unit connected to the bus control device and requiring serial data communication need to be installed apart from the bus control device. When a distance is lengthened, communication rate is lowered as a result. Since there is a communication rate difference between the serial communication type I/O interface for the internal I/O unit connected to the inside of the bus control device and the external I/O unit, the communication rate for the internal I/O unit has to be lowered. An object of the present invention is to provide a bus control system in which after analyzing header information including a destination address to switch a transmission rate, transmission from an I/O unit is waited for with a reception clock corresponding to the same transmission rate, and transmission/reception can be performed with I/O units corresponding to different transmission rates.
Problem 4: There are a plurality of external I/O units connected to the bus control device and requiring serial data communication. The large number of signal conductors enlarges the connector space, complicates the cable wiring, and prevents the miniaturization of the bus control device. An object of the present invention is to provide a bus control system in which a bus control device is provided with an inventive interface to share a communication line of a drive controller with another external I/O unit, so that a connecting connector space is reduced and a cable wiring is simplified.
In a bus control device of the present invention, a local CPU controls a serial bus transmission/reception controller for sending a transmission timing to a transmission interface for reading a predetermined transmission data from a memory with destination addresses of a plurality of units connected to a serial bus. The transmission/reception data is transferred with the plurality of units stored in the memory to form a transmission frame. The frame is transmitted to the serial bus in such a manner that transmission/reception is performed with units connected to the serial bus out of the plurality of units via the serial bus. The destination address and transmission data are read from the memory during transmission, and received data is written to the memory during reception. Therefore, the transmission is automatically made to other units in accordance with the preset transmission timing, and the data received from the other units is automatically stored in the memory, so that the received data on the memory can be read in accordance with a control cycle. Moreover, communication can be performed to the unit connected to the bus control device by requiring cyclic data transfer via the serial bus. As a result, the data traffic amount of the parallel bus can be reduced to enhance the performance of the bus control device.
Moreover, in the bus control device of the present invention, the local CPU and CPU provided on the unit read/write data stored in the memory via the transmission or reception interface. As a result, the local CPU and the CPU provided on the unit could read input data received on the memory from the other units in accordance with a single control cycle.
Furthermore, in the bus control device of the present invention, the transmission and reception interfaces connected to a first serial bus perform a cyclic transmission/reception, while the transmission and reception interfaces connected to a second serial bus perform an asynchronous message transmission/reception. In this case, the second serial bus can be used for a large number of purposes without being interrupted by the cyclic transmission/reception.
Moreover, in the bus control device of the present invention, the transmission interface connected to the second serial bus transmits the transmission frame including header information designating individual units connected to the second serial bus. The transmission frame includes header information for performing broadcast communication to simultaneously notify the units connected to the second serial bus of the message. In this case, a simultaneous broadcast function can be realized by the second serial bus.
Furthermore, in the bus control device of the present invention, when the transmission frame with the header information for performing broadcast communication added thereto is transmitted to the second serial bus, the communication by the first serial bus is cut off. In this case, when the broadcast communication is a notification of abnormality, the communication of the first serial bus is cut off, and the connected unit performs output OFF operation at the time of the abnormality. Therefore, the safety of the system can be enhanced.
Moreover, in the bus control system of the present invention, a transmission address comparator compares destination unit addresses, and outputs a signal indicating whether the transmission frame is to be transmitted to a high-speed serial bus or a low-speed serial bus. A transmission change-over switch selects either the high-speed serial bus or the low-speed serial bus to output the transmission frame in response to the output signal of the transmission address comparator. In this case, the transmission rate inside the bus control device can be set without considering the distance of the low-speed serial bus used to connect the external unit. The result is that the transmission rate to an internal unit connected to the high-speed serial bus does not need to be lowered. Thus, the communication performance for the internal unit of the bus control device can be enhanced.
Furthermore, in the bus control system of the present invention, a serial bus transmission controller performs a rate switching of high-speed transmission and low-speed transmission in accordance with a comparison result of the destination unit addresses. The transmission interface transmits to the high-speed serial bus the transmission frame formed by reading predetermined transmission data from the memory at the transmission rate in response to the rate switching. When the transmission rate of the transmission frame transmitted from the high-speed serial bus is low, a low-speed serial bus controller provided between the high-speed serial bus and the low-speed serial bus transmits the transmission frame to the low-speed serial bus. In this case, since the transmission rate inside the bus control device can be set without considering the influence of the distance of the external unit connected to the low-speed serial bus, the transmission rate of the external/internal unit does not need to be lowered. Furthermore, the communication performance for the unit inside the bus control device can be enhanced.
Additionally, in the bus control system of the present invention, high-speed transmission is performed for a drive controller requiring a machine high-speed, high-precision control, while low-speed transmission can be performed for a remote I/O unit sufficient with a relatively low speed and installed remotely from the bus control device. Therefore, a flexible system can be constructed without lowering the performance of the drive controller requiring the high-speed transmission.
Moreover, in the bus control system of the present invention, when the transmission interface performs a time division transmission for the drive controller and remote I/O unit, the bus control device can perform the control of the drive controller without being interrupted.
Furthermore, in the bus control system of the present invention, the transmission interface of a serial bus control device transmits to the serial bus the transmission frame formed by reading the predetermined transmission data from the memory. The transmission interface further controls the timing for transmission to the other units in a time zone in which no transmission is made to one unit via the serial bus. The reception interface monitors the serial bus, receives a reception frame including the header information of the device, and writes the data in a predetermined address of the memory. In this case, the serial bus can be shared in the communication for the one and other units, and the one and other units do not require individual cables or connectors. Therefore, the bus control device can be miniaturized, and the cable wiring can be simplified.
Additionally, in the bus control system of the present invention, the bus control device performs transmission to the remote I/O unit in a time period during which the mechanical high-speed, high-precision drive controller makes no transmission. Therefore, a flexible system can be constructed without lowering the performance of the drive controller which has to transmit/receive much information.
Moreover, in the bus control system of the present invention, the bus control device receives data from a servo amplifier/inverter unit in a time period during which no transmission requiring mechanical high-speed, high-precision control is made to the drive controller. Thus, a flexible system can be constructed without lowering the performance of the drive controller which has to transmit/receive much information.
Furthermore, in the bus control system of the present invention, a serial receiver of the servo amplifier/inverter unit outputs a synchronous signal when the transmission frame transmitted to the drive controller by the bus control device is normal. A predetermined time behind the output of the synchronous signal, the servo amplifier/inverter unit transmits position information of another motor to the reception interface. Therefore, the serial bus can be shared without interrupting the communication of the bus control device and the drive controller.
Additionally, in the bus control system of the present invention, the bus control device receives data from a sensor input unit in the time period in which no transmission requiring the machine high-speed, high-precision control is made to the drive controller. As a result, a flexible system can be constructed without lowering the performance of the drive controller which has to transmit much information.
Moreover, in the bus control system of the present invention, a serial receiver of the sensor input unit outputs a synchronous signal when the transmission frame transmitted to the drive controller by the bus control device is normal. Then, a deviation amount between a synchronous signal output timing and a sensor input timing is transmitted to the reception interface. Therefore, the bus control device is able to determine the time when a sensor input is made while a command is repeatedly transmitted to the drive controller.